1. Field of Invention
Embodiments disclosed herein relate generally to semiconductor devices and, more particularly, to a semiconductor device having stacked transistors and a method of forming the same.
2. Description of the Related Art
Most recent electronic appliances include semiconductor devices that include electronic elements such as a transistor, a resistor, and a capacitor. The electronic elements are designed and manufactured to perform expected functions and are then integrated together on a semiconductor substrate. For example, the electronic appliances such as a computer and a digital camera include semiconductor devices such as a memory chip for storing information and a processing chip for controlling information. The memory chip and the processing chip include electronic elements integrated on a semiconductor substrate.
On the other hand, semiconductor devices need to be more highly integrated to satisfy consumers with an excellent performance and a reasonable price. Conventionally, electronic elements constituting a semiconductor device are miniaturized to achieve high integration. However, because of various technical limitations in semiconductor device manufacturing processes, a developing speed of miniaturizing the electronic elements is under certain restriction. Accordingly, a new semiconductor device manufacturing method for overcoming the miniaturization limitation is required to achieve the desired integration of the semiconductor device.
Lately, as a corresponding method of manufacturing a highly integrated semiconductor device, there is provided a method of stacking transistors in a plurality of layers. FIG. 1 is a sectional view of a conventional semiconductor device having stacked transistors.
Referring to FIG. 1, a conventional semiconductor device 10 includes a plurality of first transistors 12 on a semiconductor substrate 11 having a device isolation layer 11′. The first transistor 12 includes source/drain regions 12′. A first interlayer insulation layer 13 covers the first transistors 12 on the semiconductor substrate 11. A semiconductor layer 14 formed from a seed plug 13′ is on the first interlayer insulation layer 13. Second transistors 15 are provided on the semiconductor layer 14, and a second interlayer insulation layer 16 is provided on the second transistors 15. The second transistor 15 includes source/drain regions 14′. A conducting column 17 penetrates the source/drain regions 14′ of the semiconductor layer 14 and the second and first interlayer insulation layers 16 and 13 to contact the semiconductor substrate 11. The semiconductor substrate 11 is electrically connected to the second transistors 15 via the semiconductor layer 14 and the conducting column 17.
Typically, the semiconductor layer 14 is thinly formed to reduce a leakage current of the second transistors 15. However, when the semiconductor layer 14 is thin, a contact area “A” between the conducting column 17 and the source/drain regions 14′ of the semiconductor layer 14 decreases. Therefore, contact resistance increases and semiconductor device characters deteriorate.